Most Commonly Asked VLSI Interview Questions and Answers

Q1. What is meant by VLSI?

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Q2. What is boolean logic and how do you use it?

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Boolean logic is a core element of VLSI and microchip development, so this is a question you can expect to hear. Since it relates to Boolean algebra, you might also mention that in your response to further demonstrate your knowledge.

Q3. What is Verilog?

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Verilog is an HDL (Hardware Description Language) for describing electronic circuits and systems.  In Verilog, circuit components are prepared inside a Module.  It contains both behavioral and structural statements.  Structural statements signify circuit components like logic gates, counters and micro-processors. Behavioral statements represent programming aspects like loops, if-then statements and stimulus vectors.

Q4. What are the two types of procedural blocks in Verilog?

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The two types of procedural blocks in Verilog are

• Initial: Initial blocks runs only once at time zero
• Always: This block loop to execute over and again and executes always, as the name suggests

Q5. How logical gates are controlled by Boolean logic?

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In Boolean algebra, the true state is denoted by the number one, referred as logic one or logic high. While, the false state is represented by the number zero, called logic zero or logic low.  And in the digital electronic, the logic high is denoted by the presence of a voltage potential.

Q6. What are the different gates where Boolean logic are applicable?

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• NOT Gate: It has one out input and one output. For example, if the value of A= 0 then the Value of B=1 and vice versa
• AND Gate: It has one output due to the combination of two output. For example, if the value of A and B= 1 then value of Q should be 1
• OR Gate: Either of the value will show the same output. For example, if the value of A is 1 or B is 0 then value of Q is 1

These are the basic three types of gates where Boolean logic work, apart from these, other gates that are functional works with the combination of these three basic gates, they are XNOR gate, NAND gate, Nor gate and XOR gate.

Q7. What is the difference between the TTL chips and CMOS chips?

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Q8. Explain how Verilog is different to normal programming language?

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Verilog can be different to normal programming language in following aspects

• Simulation time concept
• Multiple threads
• Basic circuit concepts like primitive gates and network connections

Q9. Why present VLSI circuits use MOSFETs instead of BJTs?

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In comparison to BJT, MOSFETS can be made very compact as they occupy very small silicon area on IC chip and also in term of manufacturing they are relatively simple. Moreover, digital and memory ICs can be employed with circuits that use only MOSFETs, i.e., diodes, resistors, etc.

Q10. Mention what are three regions of operation of MOSFET and how are they used?

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MOSFET has three regions of operations

• Cut-off region
• Triode region
• Saturation region

The triode and cut-off region are used to function as a switch, while, saturation region is used to operate as an amplifier.

Q11. What is the depletion region?

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When positive voltage is transmitted across Gate, it causes the free holes (positive charge) to be pushed back or repelled from the region of the substrate under the Gate. When these holes are pushed down the substrate, they leave behind a carrier depletion region.

Q12. Why is the number of gate inputs to CMOS gates usually limited to four?

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Higher the number of stacks, slower the gate will be.  In NOR and NAND gates the number of gates present in the stack is usually alike as the number of inputs plus one. So input are restricted to four.

Q13. What is SCR (Silicon Controlled Rectifier)?

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SCR is a 4 layered solid state device which controls current flow.  It is a type of rectifier that is controlled by a logical gate signal. It is a 4 layered, 3-terminal device.

Q14. What is the use of defpararm?

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With the keyword defparam, parameter values can be configured in any module instance in the design.

Q15. What is the meaning of "the channel is pinched off"?

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For a MOSFET, when the voltage value between Gate and Source (VGS) is greater than the threshold voltage (Vt), the channel is induced. As we increase, VDS current starts flowing from Drain to Source till the voltage between gate and channel at the drain end becomes Vt, i.e., VGS - VDS = Vt, the channel depth at Drain end decreases almost to zero. At this stage, the channel is said to be pinched off. In this condition, the MOSFET enters the saturation region.

Q16. What does the "timescale 1 ns/ 1 ps" specify in Verilog code?

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In Verilog code, "the timescale 1 ns/ 1 ps" specifies that the unit of time is 1 ns, and the accuracy/precision will be upto 1ps.

Q17. What are the different types of skews used in VLSI?

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In the clock, a skew is used to reduce the delay or better understand the process. There are mainly three different types of skews used in VLSI.

• Local skew: The local skew is generally used to include the difference between the launching flip-flop and the destination flip-flop. This differentiation helps to define a time path between the two.
• Global skew: The global skew defines the difference between the earliest components reaching the flip flop within the same clock domain. It needs to be mentioned in this skew. The delays are not measured while the clock is uniform for both.
• Useful skew: The useful skew is used to define the delay in capturing flip flop paths, which later helps set up an environment with precise requirements for the launch and capture of the timing path. It needs to be mentioned for design purposes to met the hold requirements.

Q18. How many transistors do a static RAM use?

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Generally, a static RAM makes use of six transistors. Under the static RAM, read and write operations make use of the same port.

Q19. What do you understand by the threshold voltage?

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The threshold voltage is commonly abbreviated as V??. It can be defined as a voltage between Gate and Source, i.e., VGS. A sufficient number of mobile electrons accumulate in the channel region and create a conducting channel. It is the minimum gate-to-source voltage required to create a conducting path between the source and the drain terminals. It is an essential scaling factor to maintain power efficiency.

Q20. What are the different ways to prevent Antenna Violation?

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Antenna violation occurs during plasma etching when the charges generated from one metal strip to another accumulate in a single place. The length of the strip is directly proportional to the charges gets accumulated. Therefore, the longer the strip, the more the charges get accumulated.

We can prevent Antenna Violation by using the following methods:

• First, by creating jogging, the metal line consists of at least one metal above the protected layer.
• We have to jog the metal to get the etching effect. This step is taken because if metal gets the etching, the other metal gets disconnected if we don't take the prevention measures.
• We can also prevent it by adding the reverse diodes at the gates that are used in the circuits.

Q21. What is the function of tie-high and tie-low cells?

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The tie-high and tie-low cells are used to connect the transistors of the gate by using either the power or the ground. The gates are connected using the power or ground to turn off and on them because the power bounces from the ground. The cells stop the bouncing and ease the current from one cell to another. These cells require Vdd that connects to the tie-high cell as a power supply is high, and tie-low gets connected to Vss. After the connection establishment, the transistors function correctly without any ground bounce occurring in any cell.

Q22. What is the range of integration can be designed using VLSI technology?

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VLSI technology can incorporate ICs in a range of 2000 to 20,000.

Q23. What is Moore’s law?

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Moor’s law is one of the most significant statements that describes large-scale integration technology growth. Gordon Moor, the co-founder of Intel, predicted that the number of transistors inside an integrated cheap would be doubled every 1.5 years.

Q24. What is Antenna Effect regarding VLSI technology?

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While the fabrication of interconnection is under process, some of the metal lines may be partially processed. Those metal lines further gather static charges inside the clot surroundings. Later, if those lines get interconnected with transistors, the previously stored charges may start discharging during operation in progress. That discharging may affect the gate oxide. This effect is known as Antenna Effect.

Q25. What is PLL?

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PLL is Phase Locked Loop, which can track the frequency- coming inside. PLL can also work as a clock generator.

Q26. How many MOSFETs and BJTs are required to design a BiCMOS two-input NAND gate? Draw the circuit diagram of a two-input BiCMOS NAND gate.

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To build a BiCMOS two-input NAND gate, we need 7 MOSFETs and 2 BJTs.

BiCMOS NAND Gate

Q27. How many MOSFETs and BJTs are required to design a BiCMOS two-input NOR gate? Draw the circuit diagram of a BiCMOS NOR gate.

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To build a BiCMOS two-input NOR gate, we need 7 MOSFETs and 2 BJTs.

BiCMOS NOR Gate

Q28. What is ROBDD and OBDD?

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OBDD is an Ordered Binary Decision Diagram, and ROBDD is Reduced Ordered Decision Diagram. These are Boolean space methodology for handling a large number of input signals.

Q29. Give some examples of Logic Synthesis Techniques of VLSI design.

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Some of the logic synthesis techniques are – Instantiation, Macro expansion/ substitution, Inference, logic optimization, and structural reorganization.

Q30. Describe Slew Balancing.

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Slew is a basic term related to the rise and fallen time of the input and output waveforms. Rise time is known as rising slew, whereas fall time is known as fall slew. Slew balancing is the process of making the rise slew and fall slew equal. To do so, the corresponding resistances of the transistors are kept equal.

Q31. What are the future technologies of VLSI?

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Future technologies of VLSI are – ULSI (Ultra Large Scale Integration) and GSI (Giga- Scale Integration). ULSI has a range of – 100,000 gates to 1,000,000 gates per IC, and GSI has a range greater than 1,000,000 gates per IC.